1. Field of the Invention
The present invention relates generally to Direct Memory Access (DMA) control and, more particularly, providing a mechanism for maintaining command ordering in a DMA control unit.
2. Description of the Related Art
In conventional systems, a Direct Memory Access (DMA) unit is a device that is capable of directly accessing memory, therefore bypassing a main processor. This type of system exists in some bus architectures. However, in order to have an efficient and orderly usage of the DMA unit in a system, there must be controls and limitations placed on DMA usage of memory.
A DMA Unit performs control of the DMA usage. Typically, a request or command for memory usage to the DMA Unit is made. The DMA Unit will act as a virtual gatekeeper to allow the requests or commands to be executed in an orderly fashion. However, there can be a number of DMA units that make requests or commands, a number of commands by a single DMA unit, or any combination thereof. To alleviate the problem of multiple requests clogging a system, a DMA Unit employs a queue to store the series of DMA unit requests or commands.
Typically, the series of DMA unit requests or commands are executed in the order in which the requests or commands arrive at the DMA Unit or are executed in a strict order. However, the strict order can be quite costly. There are a variety of problems that can arise as a result of strict order. For example, a high priority DMA command can be delayed by a low priority DMA command.
Another reason a strict ordering rule is quite costly is when virtual memory system is used for the DMA. If the translation from Virtual address to Real address is not available, the DMA unit must wait until the translation miss is resolved. Sometimes the translation miss can be resolved by hardware and other times the miss must be resolved by software. In either case, the latency of resolving the translation fault is very long. There are other cases, such as a DMA to or from a slow device will prevent DMA Commands further back in the queue with no dependencies on the present DMA command from being executed.
For loads and stores, some conventional systems, such as the PowerPC®, have been able to improve performance through the use of a weakly ordered or weakly consistent memory model. The concept of weakly ordered memory models can be extended to the execution of DMA commands. In the weakly ordered model for DMA Units, tags are associated with each command. The commands are completed in any order. However, the tags allow control software to monitor the order and group associated or dependant commands.
Allowing the completion of commands in any order, though, poses a number of problems. For example, if there is a requirement that a command completes prior to the execution of a subsequent command. Therefore, there is a need for a method and/or apparatus for ordering DMA commands that addresses at least some of the problems associated with conventional methods and apparatuses for executing DMA commands.